Memory system, memory controller and memory device for configuring super blocks

ABSTRACT

A memory system, a memory controller and a memory device are provided. The memory controller groups a first set of a plurality of memory blocks into a first super block, and a number of memory dies corresponding to the first super block is less than a number of memory dies corresponding to one channel and the number of memory dies corresponding to the first super block is determined differently depending on which of one or more control parameters are received by the memory controller. Through this, it is possible to provide a memory system, a memory controller and a memory device which can flexibly configure a super block while improving the performance of a read, program or erase operation for the super block.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.16/687,000 filed on Nov. 18, 2019, which claims benefits of priority ofKorean Patent Application No. 10-2019-0057230 filed on May 15, 2019. Thedisclosure of each of the foregoing application is incorporated hereinby reference in its entirety.

BACKGROUND 1. Technical Field

Various embodiments generally relate to a memory system, a memorycontroller and a memory device.

2. Related Art

A memory system stores data based on a request of a host, such as acomputer, a mobile terminal such as a smartphone and a tablet, or any ofvarious other electronic devices. The memory system may be of a typethat stores data in a magnetic disk, such as a hard disk drive (HDD), orof a type that stores data in a nonvolatile memory, such as a solidstate drive (SDD), a universal flash storage (UFS) device or an embeddedMMC (eMMC) device.

The memory system may include a memory device configured as a magneticdisk or a nonvolatile memory, and may further include a memorycontroller for controlling the memory device. The memory controller mayreceive a command from the host, and may perform or control an operationfor reading, writing or erasing data with respect to the memory devicebased on the received command.

The memory device may include a plurality of memory blocks, and thememory system may group the plurality of memory blocks into a pluralityof super blocks. The memory system may efficiently manage the pluralityof memory blocks by managing the memory device in units of super blocks.

SUMMARY

Various embodiments are directed to a memory system, a memory controllerand a memory device which can flexibly configure a super block whileimproving the performance of a read, program or erase operation for thesuper block.

Also, various embodiments are directed to a memory system, a memorycontroller and a memory device which can increase the efficiency of abackground operation such as garbage collection or wear leveling.

In one aspect, embodiments of the disclosure may provide a memory systemincluding: a memory device including a plurality of memory diesincluding respective groups of memory blocks, which collectively definea plurality of memory blocks in the memory device; and a memorycontroller configured to control the memory device.

The memory device may include a plurality of memory dies, and at leasttwo of the plurality of memory dies may correspond to one channel.

The memory controller may group a first set of the plurality of memoryblocks into a first super block.

The plurality of memory blocks may include one or more first memoryblocks and one or more second memory blocks.

The first super block may include at least one first memory block and atleast one second memory block.

A first memory die which includes at least one first memory block and asecond memory die which includes at least one second memory block may bedifferent from each other.

A number of memory dies corresponding to the first super block may beless than a number of memory dies corresponding to the channel, and thenumber of memory dies corresponding to the first super block may bedetermined differently depending on which of one or more controlparameters are received by the memory controller.

The memory controller may group a second set of the plurality of memoryblocks into a second super block different from the first super block. Anumber of memory blocks in the first super block may be different from anumber of memory blocks in the second super block.

At least one of the one or more control parameters may be dynamicallyindicated by a command received from a host.

The one or more control parameters may include a maximum power budgetinformation on the memory device.

The one or more control parameters may include at least one of a maximumdata communication speed between the memory controller and a host and amaximum data communication speed between the memory controller and thememory device.

The one or more control parameters may further include one or more of aprogram time, a read sensing time and a data output time of each of thememory blocks in the first super block.

The number of memory dies corresponding to the first super block may bedetermined differently depending on a value obtained by weighting theprogram time with a first weight, and a value obtained by weighting theread sensing time with a second weight.

The first weight and the second weight may be determined by a controlratio that varies depending on a ratio of a program operation count to aread operation count for the first super block for a specific amount oftime or a ratio of a program data size to a read data size for the firstsuper block for the specific amount of time.

The number of memory dies corresponding to the first super block mayvary depending on the program time regardless of the read sensing time,when the control ratio is equal to or greater than a first thresholdratio.

The number of memory dies corresponding to the first super block mayvary depending on the read sensing time regardless of the program time,when the control ratio is equal to or less than a second thresholdratio. The second threshold ratio may be less than the first thresholdratio.

In another aspect, embodiments of the disclosure may provide a memorycontroller including: a memory interface configured to communicate witha memory device including a plurality of memory dies includingrespective groups of memory blocks, which collectively define aplurality of memory blocks in the memory device; and a control circuitconfigured to control the memory device.

The memory device may include a plurality of memory dies and at leasttwo of the plurality of memory dies may correspond to one channel.

The control circuit may group a first set of the plurality of memoryblocks into a first super block.

The plurality of memory blocks may include one or more first memoryblocks and one or more second memory blocks.

The first super block may include at least one first memory block and atleast one second memory block.

A first memory die which includes at least one first memory block and asecond memory die which includes at least one second memory block may bedifferent from each other.

A number of memory dies corresponding to the first super block may beless than a number of memory dies corresponding to the channel, and thenumber of memory dies corresponding to the first super block may bedetermined differently depending on which of one or more controlparameters are received by the control circuit.

The control circuit may group a second set of the plurality of memoryblocks into a second super block different from the first super block. Anumber of memory blocks in the first super block may be different from anumber of memory blocks in the second super block.

The one or more control parameters may include at least one of a maximumdata communication speed between the memory controller and a host and amaximum data communication speed between the memory controller and thememory device.

The one or more control parameters may further include one or more of aprogram time, a read sensing time and a data output time of each of thememory blocks in the first super block.

The number of memory dies corresponding to the first super block may bedetermined differently depending on a value obtained by weighting theprogram time with a first weight, and a value obtained by weighting theread sensing time with a second weight.

In still another aspect, embodiments of the disclosure may provide amemory device including: a plurality of memory blocks, wherein thememory device includes a plurality of memory dies each includingrespective groups of memory blocks, which collectively define aplurality of memory blocks of the memory device.

At least two of the plurality of memory dies may correspond to onechannel.

The plurality of memory blocks may include one or more first memoryblocks and one or more second memory blocks, and a first set of theplurality of memory blocks may be grouped into a first super block.

The first super block may include at least one first memory block and atleast one second memory block.

A first memory die which includes at least one first memory block and asecond memory die which includes at least one second memory block may bedifferent from each other.

A number of memory dies corresponding to the first super block may beless than a number of memory dies corresponding to the channel, and thenumber of memory dies corresponding to the first super block may bedetermined differently depending on which of one or more controlparameters are applied.

A second set of the plurality of memory blocks may be grouped into asecond super block different from the first super block, and a number ofmemory blocks in the first super block may be different from a number ofmemory blocks in the second super block.

The one or more control parameters may include at least one of a maximumdata communication speed between a memory controller and a host and amaximum data communication speed between the memory controller and thememory device.

The one or more control parameters may further include one or more of aprogram time, a read sensing time and a data output time of each of thememory blocks in the first super block.

The number of memory dies corresponding to the first super block may bedetermined differently depending on a value obtained by weighting theprogram time with a first weight, and a value obtained by weighting theread sensing time with a second weight.

In still another aspect, embodiments of the disclosure may provide amemory system including: a memory device including plural dies eachhaving plural memory blocks and a controller.

The controller may configure a super block by selecting at least one ofthe memory blocks from each of a specific number of dies, which specificnumber is at least two.

The controller may determine the specific number of dies based on one ormore pieces of information.

The pieces of information may include a maximum power budget of thememory device.

The pieces of information may include a communication speed between thecontroller and a host.

The pieces of information may include a communication speed between thecontroller and the memory device.

The pieces of information may include an operation-based time (e.g.program time/read sensing time/data output time) of a memory block inthe super block.

The embodiments of the disclosure may provide a memory system, a memorycontroller and a memory device which can flexibly configure a superblock while improving the performance of a read, program or eraseoperation for the super block.

Also, the embodiments of the disclosure may provide a memory system, amemory controller and a memory device which can increase the efficiencyof a background operation such as garbage collection or wear leveling.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram schematically illustrating a memory system inaccordance with an embodiment of the disclosure.

FIG. 2 is a block diagram schematically illustrating a memory device inaccordance with an embodiment of the disclosure.

FIG. 3 is a diagram schematically illustrating a memory block of thememory device in accordance with an embodiment of the disclosure.

FIG. 4 is a diagram illustrating configuring super blocks in the memorysystem in accordance with an embodiment of the disclosure.

FIG. 5 is a diagram illustrating a representation of another example ofconfiguring super blocks in the memory system in accordance with anembodiment of the disclosure.

FIG. 6 is a diagram illustrating control parameters for determining thenumber of memory dies corresponding to a super block in the memorysystem in accordance with an embodiment of the disclosure.

FIG. 7 is a diagram illustrating an operation in which some controlparameters are indicated by a command received from a host, inaccordance with an embodiment of the disclosure.

FIGS. 8 to 10 are diagrams to assist in the explanation of examples, ineach of which the number of memory dies corresponding to a super blockis determined by at least one control parameter, in accordance withembodiments of the disclosure.

FIGS. 11 and 12 are diagrams to assist in the explanation of examples,in each of which the number of memory dies corresponding to a superblock is determined depending on a characteristic of an operationperformed for the super block, in accordance with embodiments of thedisclosure.

FIG. 13 is a flow chart to assist in the explanation of the operationmethod illustrated in FIG. 12.

FIG. 14 is a block diagram schematically illustrating a computing systemin accordance with embodiments of the disclosure.

DETAILED DESCRIPTION

Various embodiments of the disclosure are described in detail below withreference to the accompanying drawings. In the following description,the same elements are designated by the same reference numeralsthroughout the drawings. Further, in the following description of thedisclosure, well-known technical information may be omitted so as not toobscure features and aspects of the present invention. Also, open-endedterms such as “comprising,” “having,” “including” and the like, used inthe description and claims, should not be interpreted as beingrestricted to the stated elements or operations, unless specificallystated otherwise. Where an indefinite or definite article is used inreferring to a singular noun, e.g. “a,” “an,” “the,” this may include aplural of that noun unless specifically stated otherwise.

Also, in describing the components of the disclosure, there may be termsused like first, second, A, B, (a), and (b). These are solely for thepurpose of differentiating one component from the other but not to implyor suggest the substances, order, sequence or number of the components.

In describing positional relationships of components, the terms“connected,” “coupled” or “linked,” may indicate that components aredirectly or indirectly “connected,” “coupled” or linked.

In describing time flow relationships of operations or events using, forexample, “after,” “following,” “next” or “before,” non-continuous casesmay be included unless “immediately” or “directly” is used.

In the case where a numerical value for a component or its correspondinginformation (e.g., level, etc.) is mentioned, even though there is noseparate explicit description, the numerical value or its correspondinginformation can be interpreted as including an error range that may becaused by various factors (for example, a process variable, an internalor external shock, noise, etc.).

A memory system, a memory controller and a memory device are describedbelow in detail with reference to the accompanying drawings throughvarious embodiments of the disclosure. Throughout the specification,reference to “an embodiment” or the like is not necessarily to only oneembodiment, and different references to any such phrase are notnecessarily to the same embodiment(s).

FIG. 1 is a block diagram schematically illustrating a memory system100.

Referring to FIG. 1, the memory system 100 may include a memory device110 which stores data, and a memory controller 120 which controls thememory device 110.

The memory device 110 includes a plurality of memory blocks and operatesin response to the control of the memory controller 120. Operations ofthe memory device 110 may include, for example, a read operation, aprogram operation (also referred to as a write operation) and an eraseoperation.

The memory device 110 may include a memory cell array including aplurality of memory cells which store data. Such a memory cell array mayexist in a memory block.

For example, the memory device 110 may be realized by a DDR SDRAM(double data rate synchronous dynamic random access memory), an LPDDR4(low power double data rate 4) SDRAM, a GDDR (graphics double data rate)SDRAM, an LPDDR (low power DDR), an RDRAM (Rambus dynamic random accessmemory), a NAND flash memory, a vertical NAND flash memory, a NOR flashmemory, a resistive random access memory (RRAM), a phase-change memory(PRAM), a magnetoresistive random access memory (MRAM), a ferroelectricrandom access memory (FRAM) or a spin transfer torque random accessmemory (SU-RAM).

The memory device 110 may be realized in a three-dimensional arraystructure. The embodiments of the disclosure may be applied to not onlya flash memory device in which a charge storage layer is configured by aconductive floating gate but also a charge trap flash (CTF) in which acharge storage layer is configured by a dielectric layer.

The memory device 110 is configured to receive a command and an addressfrom the memory controller 120 and access a region in the memory cellarray which is selected by the address. In other words, the memorydevice 110 may perform an operation, corresponding to the command, for aregion selected by the address.

For example, the memory device 110 may perform a program operation, aread operation and an erase operation. In this connection, in theprogram operation, the memory device 110 may program data in a regionselected by the address. In the read operation, the memory device 110may read data from a region selected by the address. In the eraseoperation, the memory device 110 may erase data stored in a regionselected by the address.

The memory controller 120 may control the operation of the memory device110 according to a request of a host (HOST) 50 or regardless of arequest of the host 50.

For example, the memory controller 120 may control write (program),read, erase and background operations for the memory device 110. Forexample, the background operation may be a garbage collection (GC)operation, a wear leveling (WL) operation, a bad block management (BBM)operation, or the like.

Referring to FIG. 1, the memory controller 120 may include a hostinterface 121, a memory interface 122, and a control circuit 123.

The host interface 121 provides an interface for communication with thehost 50. When receiving a command from the host 50, the control circuit123 may receive the command through the host interface 121, and then,may perform an operation of processing the received command.

The memory interface 122 is coupled with the memory device 110 andthereby provides an interface for communication with the memory device110. That is to say, the memory interface 122 may be configured toprovide the interface between the memory device 110 and the memorycontroller 120 in response to the control of the control circuit 123.

The control circuit 123 performs the general control operations of thememory controller 120, thereby controlling the operations of the memorydevice 110. To this end, for instance, the control circuit 123 mayinclude at least one of a processor 124 and a working memory 125, and asthe case may be, may further include an error detection and correctioncircuit (ECC circuit) 126.

The processor 124 may control general operations of the memorycontroller 120, and may perform a logic calculation. The processor 124may communicate with the host 50 through the host interface 121, and maycommunicate with the memory device 110 through the memory interface 122.

The processor 124 may perform the function of a flash translation layer(FTL). The processor 124 may translate a logical block address (LBA),provided by the host 50, into a physical block address (PBA), throughthe flash translation layer (FTL). The flash translation layer (FTL) mayreceive the logical block address (LBA) and translate it into thephysical block address (PBA), by using a mapping table. There arevarious address mapping methods of the flash translation layer,depending on a mapping unit. Representative address mapping methodsinclude a page mapping method, a block mapping method and a hybridmapping method.

The processor 124 is configured to randomize data received from the host50. For example, the processor 124 may randomize data received from thehost 50, by using a randomizing seed. Randomized data to be stored isprovided to the memory device 110 and is programmed to the memory cellarray.

The processor 124 is configured to derandomize data received from thememory device 110, in a read operation. For example, the processor 124may derandomize data received from the memory device 110, by using aderandomizing seed. Derandomized data may be outputted to the host 50.

The processor 124 may control the operation of the memory controller 120by executing firmware. In other words, in order to control generaloperations of the memory controller 120 and perform a logic calculation,the processor 124 may execute (drive) firmware loaded to the workingmemory 125 upon booting. For instance, the firmware may be stored in thememory device 110 and be loaded to the working memory 125.

The firmware as a program executed in the memory system 100 may include,for example, a flash translation layer (FTL) which performs a convertingfunction between a logical address requested by the memory system 100from the host 50 and a physical address of the memory device 110, a hostinterface layer (HIL) which serves to analyze a command requested to thememory system 100 as a storage device from the host 50 and transfers thecommand to the flash translation layer (FTL), and a flash interfacelayer (FIL) which transfers a command instructed from the flashtranslation layer (FTL) to the memory device 110.

The working memory 125 may store firmware, program code, a command anddata to drive the memory controller 120.

The working memory 125, for example, as a volatile memory, may includeat least one among an SRAM (static RAM), a DRAM (dynamic RAM) and anSDRAM (synchronous DRAM).

The error detection and correction circuit 126 may be configured todetect an error bit of data stored in the working memory 125 (that is,read data transferred from the memory device 110) by using an errorcorrection code and correct the detected error bit.

The error detection and correction circuit 126 may be realized to decodedata by using an error correction code. The error detection andcorrection circuit 126 may be realized by any of various code decoders.For example, a decoder which performs unsystematic code decoding or adecoder which performs systematic code decoding may be used.

For example, the error detection and correction circuit 126 may detectan error bit for each read data, in the unit of sector. Namely, eachread data may be constituted by a plurality of sectors. A sector maymean a data unit smaller than a page as a read unit of a flash memory.Sectors constituting each read data may be matched with one another bythe medium of an address.

The error detection and correction circuit 126 may calculate a bit errorrate (BER), and may determine whether an error is correctable or not, inthe unit of sector. For example, in the case where a bit error rate(BER) is higher than a reference value, the error detection andcorrection circuit 126 may determine a corresponding sector as beinguncorrectable or a fail. On the other hand, in the case where a biterror rate (BER) is lower than the reference value, the error detectionand correction circuit 126 may determine that a corresponding sector iscorrectable or a pass.

The error detection and correction circuit 126 may perform an errordetection and correction operation sequentially for all read data. Inthe case where a sector included in read data is correctable, the errordetection and correction circuit 126 may omit an error detection andcorrection operation for a corresponding sector for next read data. Ifthe error detection and correction operation for all read data is endedin this way, the error detection and correction circuit 126 may detect asector which is determined to be uncorrectable as the last. There may beone or more sectors that are determined to be uncorrectable. The errordetection and correction circuit 126 may transfer information (forexample, an address information) on a sector, which is determined to beuncorrectable, to the processor 124.

A bus 127 may be configured to provide channels among the components121, 122, 124, 125 and 126 of the memory controller 120. The bus 127 mayinclude, for example, a control bus for transferring various controlsignals, commands and the likes, a data bus for transferring variousdata, and the like.

The above-described components 121, 122, 124, 125 and 126 of the memorycontroller 120 are illustrated by way of example only. Not all suchcomponents are necessarily needed in each embodiment, and the functionsof one or more such components may be combined into a single component.Of course, as those skilled in the art will understand, the memorycontroller 120 may include additional components not illustrated in FIG.1.

The memory device 110 is described in further detail with reference toFIG. 2 below.

FIG. 2 is a block diagram schematically illustrating the memory device110 in accordance with an embodiment of the disclosure.

Referring to FIG. 2, the memory device 110 may include a memory cellarray 210, an address decoder 220, a read and write circuit 230, controllogic 240, and a voltage generation circuit 250.

The memory cell array 210 may include a plurality of memory blocks BLK1to BLKz (z is a natural number of 2 or greater).

In the plurality of memory blocks BLK1 to BLKz, a plurality of wordlines WL and a plurality of bit lines BL may be disposed, and aplurality of memory cells (MC) may be arranged.

The plurality of memory blocks BLK1 to BLKz may be coupled to theaddress decoder 220 through the plurality of word lines WL. Theplurality of memory blocks BLK1 to BLKz may be coupled to the read andwrite circuit 230 through the plurality of bit lines BL.

Each of the plurality of memory blocks BLK1 to BLKz may include aplurality of memory cells. For example, the plurality of memory cellsmay be nonvolatile memory cells, which may have vertical channelstructures. The memory cell array 210 may be configured as atwo-dimensional structure, or as the case may be, as a three-dimensionalstructure.

Each of the plurality of memory cells included in the memory cell arraymay store at least 1-bit data. For instance, each of the plurality ofmemory cells included in the memory cell array 210 may be a signal levelcell (SLC) which stores 1-bit data. For another instance, each of theplurality of memory cells included in the memory cell array 210 may be amulti-level cell (MLC) which stores 2-bit data. For another instance,each of the plurality of memory cells included in the memory cell array210 may be a triple level cell (TLC) which stores 3-bit data. Foranother instance, each of the plurality of memory cells included in thememory cell array 210 may be a quad level cell (QLC) which stores 4-bitdata. For still yet another instance, the memory cell array 210 mayinclude a plurality of memory cells, each of which stores 5 or more-bitdata.

Referring to FIG. 2, the address decoder 220, the read and writhecircuit 230, the control logic 240 and the voltage generation circuit250 may collectively operate as a peripheral circuit which drives thememory cell array 210.

The address decoder 220 may be coupled to the memory cell array 210through the plurality of word lines WL. The address decoder 220 may beconfigured to operate in response to the control of the control logic240. The address decoder 220 may receive an address through aninput/output buffer in the memory device 110.

The address decoder 220 may be configured to decode a block address inthe received address. The address decoder 220 may select at least onememory block depending on the decoded block address. The address decoder220 may apply a read voltage Vread generated in the voltage generationcircuit 250 to a word line selected in a memory block selected in a readvoltage applying operation during a read operation, and may apply a passvoltage Vpass to the remaining unselected word lines. Further, theaddress decoder 220 may apply a verify voltage generated in the voltagegeneration circuit 250 to a word line selected in a selected memoryblock in a program verify operation, and may apply the pass voltageVpass to the remaining unselected word lines.

The address decoder 220 may be configured to decode a column address inthe received address. The address decoder 220 may transmit the decodedcolumn address to the read and write circuit 230.

A read operation and a program operation of the memory device 110 may beperformed in the unit of page. An address received when a read operationor a program operation is requested may include a block address, a rowaddress and a column address.

The address decoder 220 may select one memory block and one word linedepending on a block address and a row address. A column address may bedecoded by the address decoder 220 and be provided to the read and writecircuit 230.

The address decoder 220 may include at least one among a block decoder,a row decoder, a column decoder and an address buffer.

The read and write circuit 230 may include a plurality of page buffersPB. The read and write circuit 230 may operate as a read circuit in aread operation of the memory cell array 210, and may operate as a writecircuit in a write operation of the memory cell array 210.

The read and write circuit 230 described above may include a page buffercircuit or a data register circuit. For example, the data registercircuit may include a data buffer for performing a data processingfunction, and as the case may be, may further include a cache buffer forperforming a caching function.

The plurality of page buffers PB may be coupled to the memory cell array210 through the plurality of bit lines BL. The plurality of page buffersPB may continuously supply sensing current to bit lines coupled withmemory cells to sense the threshold voltages (Vth) of the memory cellsin a read operation and a program verify operation, and may latchsensing data by sensing, through sensing nodes, that the amounts ofcurrent flowing depending on the programmed states of the correspondingmemory cells are changed. The read and write circuit 230 may operate inresponse to page buffer control signals outputted from the control logic240.

In a read operation, the read and write circuit 230 temporarily storesread data by sensing data of memory cells, and then, outputs data DATAto the input/output buffer of the memory device 110. In an embodiment,the read and write circuit 230 may include a column select circuit inaddition to the page buffers (or page registers).

The control logic 240 may be coupled with the address decoder 220, theread and write circuit 230 and the voltage generation circuit 250. Thecontrol logic 240 may receive a command CMD and a control signal CTRLthrough the input/output buffer of the memory device 110.

The control logic 240 may be configured to control general operations ofthe memory device 110 in response to the control signal CTRL. Further,the control logic 240 may output a control signal for adjusting theprecharge potential levels of the sensing nodes of the plurality of pagebuffers PB.

The control logic 240 may control the read and write circuit 230 toperform a read operation of the memory cell array 210.

The voltage generation circuit 250 may generate the read voltage Vreadand the pass voltage Vpass in a read operation in response to a voltagegeneration circuit control signal outputted from the control logic 240.

FIG. 3 is a diagram schematically illustrating one of the plurality ofmemory blocks BLK1 to BLKz of the memory device 110 in accordance withan embodiment of the disclosure.

Referring to FIG. 3, each of the plurality of memory blocks BLK1 to BLKzmay be configured as a plurality of pages PG and a plurality of stringsSTR are disposed in the form of a matrix.

The plurality of pages PG correspond to a plurality of word lines WL,and the plurality of strings STR correspond to a plurality of bit linesBL.

That is to say, in each of the plurality of memory blocks BLK1 to BLKz,the plurality of word lines WL and the plurality of bit lines BL may bedisposed to intersect with each other. For example, each of theplurality of word lines WL may be disposed in a row direction, and eachof the plurality of bit lines BL may be disposed in a column direction.For another example, each of the plurality of word lines WL may bedisposed in a column direction, and each of the plurality of bit linesBL may be disposed in a row direction.

A plurality of memory cells MC may be defined at respectiveintersections of the word lines WL and bit lines BL. A transistor may bedisposed in each memory cell MC. For example, the transistor disposed ineach memory cell MC may include a drain, a source and a gate. The drain(or the source) of the transistor may be coupled directly or via one ormore other transistors with a corresponding bit line, the source (or thedrain) of the transistor may be coupled directly or via one or moreother transistors with a source line (which may be the ground), and thegate of the transistor may include a floating gate which is surroundedby a dielectric and a control gate to which a gate voltage is applied.

A read operation and a program operation (write operation) may beperformed in the unit of page, and an erase operation may be performedin the unit of memory block.

Referring to FIG. 3, in each of the plurality of memory blocks BLK1 toBLKz, a first select line (also referred to as a source select line or adrain select line) may be additionally disposed outside a firstoutermost word line more adjacent to the read and write circuit 230between two outermost word lines, and a second select line (alsoreferred to as a drain select line or a source select line) may beadditionally disposed outside a second outermost word line between thetwo outermost word lines.

At least one dummy word line may be disposed between the first outermostword line and the first select line. At least one dummy word line mayalso be additionally disposed between the second outermost word line andthe second select line.

FIG. 4 is a diagram illustrating configuring super blocks in the memorysystem 100 in accordance with an embodiment of the disclosure.

According to the illustration of FIG. 4, the memory device 110 mayinclude four memory dies DIE0, DIE1, DIE2 and DIE3. Each of the fourmemory dies DIE0, DIE1, DIE2 and DIE3 may include two planes PL0 andPL1, and each of the two planes PL0 and PL1 may include a plurality ofmemory blocks BLK0, BLK1, BLK2, . . . , BLKn.

Some or all of the plurality of memory dies included in the memorydevice 110 may correspond to one channel CH. According to theillustration of FIG. 4, the four memory dies DIE0, DIE1, DIE2 and DIE3correspond to one channel. That is to say, an operation (e.g.,read/program/erase) for the four memory dies DIE0, DIE1, DIE2 and

DIE3 may be performed through one channel. The number of memory diescorresponding to a particular super block (described below) may be lessthan the number of dies corresponding to a channel.

The channel CH may represent various features, such as a path used toexchange data or commands between the memory controller 120 and thememory device 110, a transmission/reception method through the pathand/or definition information (e.g., a protocol) of the path. As thecase may be, the channel CH may be included in the memory interface 122of FIG. 1.

In the case where a plurality of channels exist, operations ofexchanging data or commands may be performed in an interconnected manneramong the plurality of channels or may be performed independently foreach channel.

For instance, the memory controller 120 may sequentially exchange dataor commands with the memory device 110 through one channel at a certaintime. In this case, the memory controller 120 may not exchange data orcommands in parallel. Therefore, different memory dies corresponding toone channel may not process in parallel operations corresponding todifferent commands.

On the other hand, the memory controller 120 may exchange data orcommands with the memory device 110 independently or in parallel throughdifferent channels. Therefore, different memory dies corresponding todifferent channels may process independently or in parallel operationscorresponding to different commands.

The memory controller 120 may optionally configure a unit of operationfor an efficient operation. For example, the memory controller 120 maygroup some (which may be memory blocks in one memory die or at least twomemory dies) among the plurality of memory blocks in the memory device110, into one super block. The grouping operation may be performed bythe control circuit 123 in the memory controller 120.

The plurality of memory blocks may include at least one first memoryblock and at least one second memory block. A super block may include atleast one first memory block and at least one second memory block.

Respective memory blocks included in a super block may be physicallydifferent memory blocks, but may logically operate like one memoryblock. One super block may be a set of memory blocks in which anoperation such as read/program/erase is performed simultaneously orwithin the same time slot or in which an operation such asread/program/erase is performed in an interconnected or interrelatedmanner. Also, one super block may be a set of memory blocks in which anoperation such as read/program/erase corresponding to one command isperformed. Further, one super block may be a group of memory blockswhich are distinguished in terms of operation among a plurality ofmemory blocks.

Super block may be a unit for performing a background operation such asgarbage collection, wear leveling and read reclaim.

The memory system 100 may improve operation performance by performing aspecific operation (e.g., a program operation/an erase operation) in theunit of super block, and may efficiently manage a plurality of memoryblocks by performing a background operation such as garbage collectionor wear leveling in the unit of super block.

Referring to FIG. 4, the memory controller 120 may group some among theplurality of memory blocks in the memory device 110, into a super block#1 SBLK1, a super block #2 SBLK2 or a super block #3 SBLK3. One amongsuper blocks grouped by the memory controller 120 in this way may bereferred to as a first super block.

A specific example in which the memory controller 120 groups a superblock is as follows.

For instance, the super block #1 SBLK1 may be configured by grouping thememory block #0 BLK0 of the plane #0 PL0 of the memory die #0 DIE0, thememory block #0 BLK0 of the plane #1 PL1 of the memory die #0 DIE0, thememory block #0 BLK0 of the plane #0 PL0 of the memory die #1 DIE1, thememory block #0 BLK0 of the plane #1 PL1 of the memory die #1 DIE1, thememory block #0 BLK0 of the plane #0 PL0 of the memory die #2 DIE2 andthe memory block #0 BLK0 of the plane #1 PL1 of the memory die #2 DIE2,among the plurality of memory blocks in the memory device 110.

For another instance, the super block #2 SBLK2 may be configured bygrouping the memory block #1 BLK1 of the plane #0 PL0 of the memory die#1 DIE1, the memory block #1 BLK1 of the plane #1 PL1 of the memory die#1 DIE1, the memory block #1 BLK1 of the plane #0 PL0 of the memory die#2 DIE2, the memory block #1 BLK1 of the plane #1 PL1 of the memory die#2 DIE2, the memory block #1 BLK1 of the plane #0 PL0 of the memory die#3 DIE3 and the memory block #1 BLK1 of the plane #1 PL1 of the memorydie #3 DIE3, among the plurality of memory blocks in the memory device110.

For still another instance, the super block #3 SBLK3 may be configuredby grouping the memory block #2 BLK2 of the plane #0 PL0 of the memorydie #0 DIE0, the memory block #2 BLK2 of the plane #1 PL1 of the memorydie #0 DIE0, the memory block #2 BLK2 of the plane #0 PL0 of the memorydie #1 DIE1, the memory block #2 BLK2 of the plane #1 PL1 of the memorydie #1 DIE1, the memory block #2 BLK2 of the plane #0 PL0 of the memorydie #3 DIE3 and the memory block #2 BLK2 of the plane #1 PL1 of thememory die #3 DIE3, among the plurality of memory blocks in the memorydevice 110.

In the case where super blocks are configured in this way, the superblocks may be configured over different memory dies. In other words, inthe case where a super block includes at least one first memory blockand at least one second memory block, such memory blocks may be indifferent dies. Specifically, the super block #1 SBLK1, as can be seenfrom FIG. 4, includes memory blocks from both DIE0 and DIE1. The memorydie #0 DIE0 in which the memory block #0 BLK0 of the plane #0 PL0 isincluded and the memory die #2 DIE2 in which the memory block #0 of theplane #1 PL1 is included are different from each other.

The super blocks described above with reference to FIG. 4 include thesame number of memory blocks and are configured over the same number ofmemory dies. Specifically, each of the super block #1 SBLK1, the superblock #2 SBLK2 and the super block #3 SBLK3 includes six memory blocks,and is configured over three different memory dies. Accordingly, each ofsuper blocks #1, #2 and #3 is an example of a super block formed ofmemory blocks from a lesser number of dies than the number of dies thatcorrespond to the channel CH.

However, as illustrated in FIG. 5, super blocks may be configured insuch a manner that the numbers of memory blocks in the respective superblocks are different from one another. Furthermore, respective superblocks may be configured over different numbers of memory dies.

FIG. 5 is a diagram illustrating another example of configuring superblocks in the memory system 100 in accordance with an embodiment of thedisclosure.

Referring to FIG. 5, the numbers of memory blocks which configurerespective super blocks are different from one another. A super block #4SBLK4 includes four memory blocks, a super block #5 SBLK5 includes threememory blocks, a super block #6 SBLK6 includes six memory blocks, and asuper block #7 SBLK7 includes two memory blocks. Namely, the number ofmemory blocks in a first super block may be different from the number ofmemory blocks in a second super block different from the first superblock.

Moreover, respective super blocks are configured over different numbersof memory dies. The super block #4 SBLK4 and the super block #5 SBLK5may be configured over two memory dies, the super block #6 SBLK6 may beconfigured over three memory dies, and the super block #7 SBLK7 may beconfigured over one memory die.

Regarding super block #6 SBLK6, it may be configured in such a mannerthat indexes indicating on-plane positions of respective memory blocksare different from each other, as in the case of the memory blocks #2BLK2 and the memory blocks #3 BLK3.

When a super block is configured over different memory dies as describedabove, the number of memory dies corresponding to the super block may bedetermined as follows.

In embodiments of the disclosure, the number of memory diescorresponding to each super block may be less than the number of memorydies corresponding to one channel. The number of memory diescorresponding to a super block may be defined as the number of memorydies each of which includes at least one memory block that is alsoincluded in the super block. That is to say, the number of memory diesacross which a super block spans may be less than the number of memorydies corresponding to one channel.

Referring to FIGS. 4 and 5, the number of memory dies corresponding toone channel CH is 4, that is, the memory dies DIE0, DIE1, DIE2 and DIE3correspond to the same channel CH. However, as illustrated in FIG. 4,the number of memory dies corresponding to the super block #1 SBLK1 is 3(memory dies DIE0, DIE1 and DIE2), which is less than 4. The same istrue for super block #2 SBLK2; it includes 3 memory dies DIE1, DIE2 andDIE3, which is less than 4. Also, super block #3 SBLK3 includes 3 memorydies DIE0, DIE1 and DIE3, which is also less than 4. Similarly, asillustrated in FIG. 5, for each of the super block #4 SBLK4, the superblock #5 SBLK5, the super block #6 SBLK6, the number of memory diescorresponding thereto is less than 4.

The reason why, in the embodiments of the disclosure, the number ofmemory dies each super block spans is set to be less than the number ofmemory dies corresponding to one channel is as follows.

As described above, in one channel, the memory controller 120 and thememory device 110 may sequentially exchange data or commands. In thisregard, if processing of data or commands exchanged between the memorycontroller 120 and the memory device 110 is simultaneously performed inall memory dies corresponding to one super block, processing speed forthe data or commands increases.

Therefore, in theory, it is advantageous in terms of performance thatthe number of memory dies corresponding to one super block is the sameas the number of memory dies corresponding to one channel.

However, in this case, if the number of memory dies corresponding to onesuper block is greater than or equal to a specific value, a performanceimprovement effect is not induced even though the number of memory diescorresponding to the super block is increased. This is because a size ofdata or commands exchanged between the memory controller 120 and thememory device 110 for a specific amount of time through one channel islimited.

In addition, if the number of memory dies corresponding to one superblock increases, power consumption amount for a specific amount of timealso increases since the number of memory dies simultaneously activatedincreases. In this case, a problem may be caused in that an amount ofpower used by the memory device 110 exceeds a maximum power consumptionlimit for the memory device 110 to perform an operation such asread/program/erase for a specific amount of time.

Also, since, as described above, a background operation such as garbagecollection or wear leveling is performed in the unit of super block, atime required for performing the background operation increases as thenumber of memory dies corresponding to one super block increases.Moreover, since the number of memory blocks to or from which data ismoved while performing garbage collection or wear levelingproportionally increases as the number of memory dies corresponding toone super block increases, a problem may be caused in that the lifetimeof the memory device 110 decreases.

Therefore, in the embodiments of the disclosure, the number of memorydies corresponding to a super block is set to be less than the number ofmemory dies corresponding to one channel.

The number of memory dies corresponding to a super block may bedetermined by various methods.

For instance, the number of memory dies corresponding to a super blockmay be a specific value, which may be the same for all super blocks. Asillustrated in FIG. 4, each super block spans or corresponds to 3 memorydies, which is less than the 4 memory dies corresponding to the channelCH.

However, as illustrated in FIG. 5, the number of memory diescorresponding to a super block may be different for each super block. Inthis regard, the number of memory dies corresponding to each super blockmay be differently determined depending on at least one controlparameter (CP).

FIG. 6 is a diagram illustrating control parameters CP for determiningthe number of memory dies corresponding to a super block SBLK in thememory system 100 in accordance with an embodiment of the disclosure.

Referring to FIG. 6, when the memory controller 120 configures a superblock SBLK, the number of memory dies corresponding to the super blockSBLK_DIE_NUM_IN_SBLK may be determined by one or more control parametersCP.

For example, such control parameters CP may include at least one among apower budget information PWR_BUDGET of the memory controller 120, amaximum data communication speed MAX_DCS_CH between the memorycontroller 120 and the host 50, a program time tPROG, a read sensingtime tR, and the like. The memory controller 120 may determine thenumber of memory dies corresponding to the super blockSBLK_DIE_NUM_IN_SBLK, by using the one or more control parameters CP,and may configure the super block SBLK based on the determined numberDIE_NUM_IN_SBLK. According to this fact, a size of the super block SBLKin terms of the number of dies that it spans may be determined.

Values of the control parameters CP may be indicated in various ways.For instance, values of control parameters CP may be values (e.g., theprogram time tPROG and the read sensing time tR) set in advance in aprocess in which the memory system 100 is manufactured. In this case,the values of the control parameters CP may be indicated by firmware forthe memory system 100.

For another instance, control parameters CP may be values that aredynamically indicated by the host 50 or an external sensor.

With reference to FIG. 7, a case where some among the control parametersCP are dynamically indicated from the host 50 is described. In general,a dynamically indicated CP represents a parameter of the memory systemthat dynamically changes depending on the operating conditions. The host50 recognizes these changes in operating conditions and changes thedynamically indicated CP accordingly.

FIG. 7 is a diagram illustrating an operation in which some among thecontrol parameters CP are indicated by a command received from the host50, in the memory system 100 in accordance with an embodiment of thedisclosure.

Referring to FIG. 7, the host 50 may transmit a command indicating acontrol parameter CP described above, to the memory controller 120. Thecommand may include a control parameter CP for allowing the memorycontroller 120 to determine the number of memory dies corresponding to asuper block SBLK_DIE_NUM_IN_SBLK, or may include information forallowing the memory controller 120 to select (determine) a controlparameter CP (e.g., a control parameter identification information). Thememory controller 120 may check the value of a corresponding controlparameter CP in the command received from the host 50, and thereby, maydetermine the number of memory dies corresponding to the super blockSBLK DIE_NUM_IN_SBLK.

A control parameter CP indicated by the command received from the host50 may be, for example, an operation type OP_TYPE (e.g.,read/program/erase) of the command.

On the other hand, a control parameter CP indicated by the commandreceived from the host 50 may be, for another example, the number ofmemory dies corresponding to the super block SBLK DIE_NUM_IN_SBLK.

A specific example in which, in the case where a value of at least onecontrol parameter CP is indicated in various ways as described above,the number DIE_NUM_IN_SBLK is determined by the indicated controlparameter CP is described below.

FIGS. 8 to 10 are diagrams to assist in the explanation of examples, ineach of which the number of memory dies corresponding to a super blockSBLK is determined by at least one control parameter CP, in the memorysystem 100 in accordance with embodiments of the disclosure.

First, referring to FIG. 8, a control parameter CP used to determine thenumber of memory dies corresponding to the super blockSBLK_DIE_NUM_IN_SBLK may include maximum power budget informationPWR_BUDGET of the memory device 110.

The maximum power budget information PWR_BUDGET of the memory device 110means information on an amount of power consumed for the memory device110 to perform an operation such as read/program/erase for a specificamount of time.

In general, the maximum power budget information PWR_BUDGET of thememory device 110 may be a value that is set in advance depending on acharacteristic (e.g., a storage capacity/a read speed/a program speed)of the memory device 110. However, the maximum power budget informationPWR_BUDGET of the memory device 110 may be dynamically determined basedon a change in an operation voltage supplied to the memory device 110,or the like.

For instance, it is assumed that a maximum power budget of the memorydevice 110 is currently 10 and power to be consumed when one memory dieis activated is 3. In this case, the number of memory dies correspondingto the super block SBLK DIE_NUM_IN_SBLK may be 3 as the whole numberresult obtained by dividing 10 by 3.

Referring to FIG. 9, a control parameter CP used to determine the numberof memory dies corresponding to the super block SBLK_DIE_NUM_IN_SBLK mayinclude one or at least two among a maximum data communication speedMAX_DCS_CH between the memory controller 120 and the host 50, a maximumdata communication speed MAX_DCS_CM between the memory controller 120and the memory device 110, and the like.

If the maximum data communication speed MAX_DCS_CH between the memorycontroller 120 and the host 50 increases, a size of data transmittedthrough one channel for a specific amount of time increases. Therefore,the number of memory dies activated to simultaneously process the entiredata transmitted increases. Thus, if the maximum data communicationspeed MAX_DCS_CH between the memory controller 120 and the host 50increases, the number of memory dies corresponding to the super blockSBLK DIE_NUM_IN_SBLK may be increased.

Communication between the memory controller 120 and the host 50 isperformed through the host interface 121 in the memory controller 120.Hence, a maximum data communication speed between the memory controller120 and the host 50 may be referred to as a host interface speed.

On the other hand, if the maximum data communication speed MAX_DCS_CMbetween the memory controller 120 and the memory device 110 increases, asize of data processed by a memory block included in one memory die fora specific amount of time increases. Therefore, the number of memorydies necessary to be activated to simultaneously process entiretransmitted data decreases. Thus, if the maximum data communicationspeed MAX_DCS_CM between the memory controller 120 and the memory device110 increases, the number of memory dies corresponding to the superblock SBLK_DIE_NUM_IN_SBLK may be decreased conversely.

Communication between the memory controller 120 and the memory device110 is performed through the memory interface 122 in the memorycontroller 120. Hence, a maximum data communication speed between thememory controller 120 and the memory device 110 may be referred to as amemory interface speed.

Referring to FIG. 10, control parameters CP used to determine the numberof memory dies corresponding to the super block SBLK_DIE_NUM_IN_SBLK mayfurther include one or more among a program time tPROG, a read sensingtime tR and a data output time tDOUT of a memory block in the superblock SBLK.

The program time tPROG of a memory block is a time during which datainputted through a data input terminal of the memory device 110 isprogrammed to memory cells in the memory block.

The read sensing time tR of a memory block is a time during which datastored in the memory block in the memory device 110 is stored in abuffer in the memory device 110.

The data output time tDOUT of a memory block is a time during which datastored in a buffer in the memory device 110 is outputted and transmittedto the memory controller 120.

As the program time tPROG of a memory block increases, an amount of dataprogrammed in one memory block for a specific amount of time decreases.Therefore, in order to program a specific size of data in the superblock SBLK for a specific amount of time, the number of memory diescorresponding to the super block SBLK DIE_NUM_IN_SBLK may be increasedin proportion to the program time tPROG of a memory block.

On the other hand, as the read sensing time tR of a memory block or thedata output data tDOUT of a memory block increases, an amount of dataread from one memory block for a specific amount of time decreases.Therefore, in order to read a specific size of data from the super blockSBLK for a specific amount of time, the number of memory diescorresponding to the super block SBLK DIE_NUM_IN_SBLK may be increasedin proportion to the read sensing time tR or the data output time tDOUTof a memory block.

A specific example in which the number of memory dies corresponding tothe super block SBLK_DIE_NUM_IN_SBLK is determined based on the controlparameters CP described above with reference to FIGS. 9 and 10 isdescribed.

For instance, it is assumed that the maximum data communication speedMAX_DCS_CH between the memory controller 120 and the host 50 is 800MBps, the program time tPROG is 1320 us and a data capacity of onememory block is 256 KB. In this case, a maximum size of data inputtedfrom the host 50 for 1320 us is 800 MB*1320*10⁻⁶≈1.05 MB. In order toprocess the data of 1.05 MB, at least five 256 KB memory blocks indifferent memory dies are needed. Therefore, the number of memory diescorresponding to the super block SBLK_DIE_NUM_IN_SBLK may be determinedas 5.

For another instance, it is assumed that the maximum data communicationspeed MAX_DCS_CH between the memory controller 120 and the host 50 is1600 MBps, the program time tPROG is 1200 us and a data capacity of onememory block is 256 KB. In this case, a maximum size of data inputtedfrom the host 50 for 1200 us is 1600 MB*1200*10⁻⁶≈1.92 MB. In order toprocess the data of 1.92 MB, at least eight 256 KB memory blocks indifferent memory dies are needed. Therefore, the number of memory diescorresponding to the super block SBLK_DIE_NUM_IN_SBLK may be determinedas 8.

Which control parameter CP of the program time tPROG, the read sensingtime tR and the data output time tDOUT of a memory block included in thesuper block SBLK is to be used in which ratio in determining the numberof memory dies corresponding to the super block SBLK_DIE_NUM_IN_SBLK maybe changed by a characteristic of an operation to be performed for thesuper block SBLK.

For instance, if a read operation is seldom performed and a programoperation is mainly performed for the super block SBLK, the number ofmemory dies corresponding to the super block SBLK may be determinedbased on the program time tPROG.

For another instance, if a program operation is seldom performed and aread operation is mainly performed for the super block SBLK, the numberof memory dies corresponding to the super block SBLK_DIE_NUM_IN_SBLK maybe determined based on the read sensing time tR or the data output timetDOUT.

On the other hand, if a read operation and a program operation areperformed for the super block SBLK at a specific ratio, the number ofmemory dies corresponding to the super block SBLK DIE_NUM_IN_SBLK may bedetermined by appropriately reflecting the program time tPROG, the readsensing time tR or the data output time tDOUT.

FIGS. 11 and 12 are diagrams to assist in the explanation of examples ineach of which the number of memory dies corresponding to a super blockSBLK_DIE_NUM_IN_SBLK is determined depending on a characteristic of anoperation performed for the super block SBLK, in the memory system 100in accordance with embodiments of the disclosure.

Referring to FIG. 11, the number of memory dies corresponding to thesuper block SBLK_DIE_NUM_IN_SBLK may be determined differently dependingon a value obtained by weighting a program time tPROG of a memory blockin the super block SBLK, with a first weight WGT1, and a value obtainedby weighting a read sensing time tR with a second weight WGT2.

That is to say, although both the program time tPROG and the readsensing time tR are reflected in determining the number of memory diescorresponding to the super block SBLK DIE_NUM_IN_SBLK, degrees to whichthe program time tPROG and the read sensing time tR are reflected mayvary.

A method of determining the first weight WGT1 and the second weight WGT2is described with reference to FIG. 12.

Referring to FIG. 12, the first weight WGT1 and the second weight WGT2may be determined by a control ratio CR indicating which of a readoperation and a program operation is mainly performed in the super blockSBLK.

The control ratio CR may vary depending on a ratio of a programoperation count to a read operation count corresponding for the superblock SBLK for a specific amount of time. This is based on theassumption that the weight of an operation is determined based on anoperation count.

On the other hand, the control ratio CR may vary depending on a ratio ofa program data size to a read data size corresponding to the super blockSBLK for a specific amount of time. This is based on the assumption thatthe weight of an operation is determined based on a size of datacorresponding to the operation, not on an operation count.

For instance, it is assumed that, for a specific amount of time (e.g., 1s), 100 read operations have been performed for the super block SBLK and10 KB data has been read in each read operation and that 10 programoperations have been performed for the super block SBLK and 100 KB datahas been programmed in each program operation.

In this case, while the ratio of read operations performed to programoperation performed in the specific amount of time is 10, the entireread data size and the entire program data size are the same, i.e., 1000KB. In this case, the control ratio CR may be determined to be 1000KB/1000 KB=1, not 10/100=0.1.

When the above-described method is used, in the case where the weight ofa read operation is greater than or equal to a specific threshold value,it may be determined that the influence of a program operation is low.Thus, the number of memory dies corresponding to the super blockSBLK_DIE_NUM_IN_SBLK may be determined depending on the read sensingtime tR regardless of the program time tPROG associated with the programoperation.

On the other hand, in the case where the weight of a program operationis greater than or equal to a specific threshold value, it may bedetermined that the influence of a read operation is low. Thus, thenumber of memory dies corresponding to the super blockSBLK_DIE_NUM_IN_SBLK may be determined depending on the program timetPROG regardless of the read sensing time tR associated with the readoperation.

An operation method of obtaining the number of memory dies correspondingto a super block SBLK_DIE_NUM_IN_SBLK, by comparing the above-describedcontrol ratio CR with a threshold value, is described below withreference to FIG. 13.

FIG. 13 is a flow chart to assist in the explanation of the operationmethod described above with reference to FIG. 12. In an embodiment, suchmethod may be performed by the memory controller 120.

Referring to FIG. 13, at step S1310, the memory controller 120 may checka program time tPROG and a read sensing time tR of a memory block in asuper block SBLK.

At step 1320, the memory controller 120 may calculate a control ratio CRindicating which of a read operation and a program operation is mainlyperformed in the super block SBLK, as described above with reference toFIG. 12.

Thereafter, at step S1330, the memory controller 120 may determinewhether the control ratio CR is greater than a specific first thresholdratio. If the control ratio CR is greater than the first thresholdratio, it means that the weight or proportion of a program operation ishigh relative to a read operation. Thus, if the control ratio CR isgreater than the first threshold ratio (S1330-Y), at step S1331, thememory controller 120 may determine the number of memory diescorresponding to the super block SBLK DIE_NUM_IN_SBLK, differentlydepending on the program time tPROG, regardless of the read sensing timetR.

If the control ratio CR is less than the first threshold ratio(S1330-N), at step S1340, the memory controller 120 may determinewhether the control ratio CR is less than a second threshold ratio. Thesecond threshold ratio is less than the first threshold ratio. If thecontrol ratio CR is less than the second threshold ratio, it means thatthe weight or proportion of a read operation is high relative to aprogram operation. Thus, if the control ratio CR is less than the secondthreshold ratio (S1340-Y), at step S1341, the memory controller 120 maydetermine the number of memory dies corresponding to the super blockSBLK_DIE_NUM_IN_SBLK, differently depending on the read sensing time tR,regardless of the program time tPROG.

If the control ratio CR is less than the first threshold ratio but isgreater than the second threshold ratio (S1340-N), at step S1342, thememory controller 120 may determine the number of memory diescorresponding to the super block SBLK DIE_NUM_IN_SBLK, differentlydepending on the program time tPROG and the read sensing time tR.

FIG. 14 is a block diagram schematically illustrating a computing system1400 in accordance with embodiments of the disclosure.

Referring to FIG. 14, the computing system 1400 may include a memorysystem 100, a central processing unit (CPU) 1410 for controlling generaloperations of the computing system 1400, a RAM 1420 for storing data andinformation related with the operations of the computing system 1400, aUI/UX (user interface/user experience) module 1430 for providing useenvironment to a user, a communication module 1440 for communicatingwith an external device in a wired and/or wireless manner and a powermanagement module 1450 for managing power used by the computing system1400, which are electrically coupled to a system bus 1460.

The computing system 1400 may include a PC (personal computer), a mobileterminal such as a smartphone and a tablet or various electronicdevices.

The computing system 1400 may further include a battery for supplying anoperating voltage, and may further include an application chipset, agraphic-related module, a camera image processor (CIS), a DRAM and thelike. As those skilled in the art understand the computing system 1400may include other components.

The memory system 100 may include not only a device which stores data ina magnetic disk, such as a hard disk drive (HDD), but also a devicewhich stores data in a nonvolatile memory, such as a solid state drive(SDD), a universal flash storage (UFS) device and an embedded MMC (eMMC)device. The nonvolatile memory may include a ROM (read only memory), aPROM (programmable ROM), an EPROM (electrically programmable ROM), anEEPROM (electrically erasable and programmable ROM), a flash memory, aPRAM (phase-change RAM), an MRAM (magnetic RAM), an RRAM (resistiveRAM), and an FRAM (ferroelectric RAM). In addition, the memory system100 may be realized as any of various types of storage devices, and maybe mounted in various electronic devices.

By the embodiments of the disclosure described above, it is possible toprovide the memory system 100, the memory controller 120 and the memorydevice 110 which can flexibly configure a super block while improvingthe performance of a read, program or erase operation for the superblock.

Also, by the embodiments of the disclosure, it is possible to providethe memory system 100, the memory controller 120 and the memory device110 which can increase the efficiency of a background operation such asgarbage collection or wear leveling.

Although various embodiments of the disclosure have been illustrated anddescribed, those skilled in the art will appreciate in light of thepresent disclosure that various modifications, additions andsubstitutions are possible, without departing from the scope and spiritof the disclosure. Therefore, the disclosed embodiments should beconsidered in a descriptive sense only and not for limiting the scope ofthe invention. The scope of the invention is defined by the appendedclaims and their equivalents.

What is claimed is:
 1. A memory system comprising: a memory devicecomprising a plurality of memory dies comprising respective groups ofmemory blocks, which collectively define a plurality of memory blocks inthe memory device; and a memory controller configured to control thememory device, wherein at least two of the plurality of memory diescorrespond to one channel, wherein the memory controller groups a firstset of the plurality of memory blocks into a first super block, andwherein a specific number of memory dies corresponding to the firstsuper block is determined as value less than a number of memory diescorresponding to the channel in a process in which the memory system ismanufactured.
 2. The memory system according to claim 1, wherein anaddress of the first super block is mapped by a block mapping method. 3.The memory system according to claim 1, wherein the specific number ofmemory dies corresponding to the first super block is determineddifferently depending on which of one or more control parameters.
 4. Thememory system according to claim 3, wherein the one or more controlparameters comprise a maximum power budget information on the memorydevice.
 5. The memory system according to claim 3, wherein the one ormore control parameters comprise at least one of a maximum datacommunication speed between the memory controller and a host and amaximum data communication speed between the memory controller and thememory device.
 6. The memory system according to claim 5, wherein theone or more control parameters further comprise one or more of a programtime, a read sensing time and a data output time of each of the memoryblocks in the first super block.
 7. The memory system according to claim6, wherein the number of memory dies corresponding to the first superblock is determined differently depending on a value obtained byweighting the program time with a first weight and a value obtained byweighting the read sensing time with a second weight.
 8. The memorysystem according to claim 7, wherein the first weight and the secondweight are determined by a control ratio that varies depending on aratio of a program operation count to a read operation count for thefirst super block for a specific amount of time or a ratio of a programdata size to a read data size for the first super block for the specificamount of time.
 9. The memory system according to claim 8, wherein thenumber of memory dies corresponding to the first super block variesdepending on the program time regardless of the read sensing time, whenthe control ratio is greater than or equal to a first threshold ratio.10. The memory system according to claim 9, wherein the number of memorydies corresponding to the first super block varies depending on the readsensing time regardless of the program time, when the control ratio isless than or equal to a second threshold ratio, and wherein the secondthreshold ratio is less than the first threshold ratio.
 11. A memorycontroller comprising: a memory interface configured to communicate witha memory device comprising a plurality of memory dies comprisingrespective groups of memory blocks, which collectively define aplurality of memory blocks in the memory device; and a control circuitconfigured to control the memory device, wherein at least two of theplurality of memory dies correspond to one channel, wherein the controlcircuit groups a first set of the plurality of memory blocks into afirst super block, and wherein a specific number of memory diescorresponding to the first super block is determined as value less thana number of memory dies corresponding to the channel in a process inwhich the memory system is manufactured.
 12. The memory controlleraccording to claim 11, wherein the specific number of memory diescorresponding to the first super block is determined differentlydepending on which of one or more control parameters.
 13. The memorycontroller according to claim 12, wherein the one or more controlparameters comprise at least one of a maximum data communication speedbetween the memory controller and a host and a maximum datacommunication speed between the memory controller and the memory device.14. The memory controller according to claim 13, wherein the one or morecontrol parameters further comprise one or more of a program time, aread sensing time and a data output time of each of the memory blocks inthe first super block.
 15. The memory controller according to claim 14,wherein the number of memory dies corresponding to the first super blockis determined differently depending on a value obtained by weighting theprogram time with a first weight and a value obtained by weighting theread sensing time with a second weight.
 16. A memory device comprising:a plurality of memory dies comprising respective groups of memoryblocks, which collectively define a plurality of memory blocks of thememory device, wherein at least two of the plurality of memory diescorrespond to one channel, wherein a first set of the plurality ofmemory blocks are grouped into a first super block, and wherein aspecific number of memory dies corresponding to the first super block isdetermined as value less than a number of memory dies corresponding tothe channel in a process in which the memory system is manufactured. 17.The memory device according to claim 16, wherein the specific number ofmemory dies corresponding to the first super block is determineddifferently depending on which of one or more control parameters. 18.The memory device according to claim 17, wherein the one or more controlparameters comprise at least one of a maximum data communication speedbetween a memory controller and a host and a maximum data communicationspeed between the memory controller and the memory device.
 19. Thememory device according to claim 18, wherein the one or more controlparameters further comprise one or more of a program time, a readsensing time and a data output time of each of the memory blocks in thefirst super block.
 20. The memory device according to claim 19, whereinthe number of memory dies corresponding to the first super block isdetermined differently depending on a value obtained by weighting theprogram time with a first weight and a value obtained by weighting theread sensing time with a second weight.